The present invention relates to FIFO apparatus and, in particular, to the use of such apparatus in a pipeline processor arrangement.
The performance of individual submodules in a pipeline processor arrangement depends on the incoming command and/or data rate, and the complexity of operation on those commands and/or data that the submodule is required to perform. The time taken by a submodule to execute a command varies according to the complexity of the command and also to the stall direction and frequency of the downstream submodule. In those cases where the rate of execution of commands varies for two neighboring pipeline submodules, a first-in-first-out register apparatus (FIFO) of a predetermined length is usually inserted between the submodules to absorb some latencies associated with the first (upstream) submodule while the second (downstream) submodule is stalled or busy. The size of the FIFO is usually a compromise between performance and cost, unfortunately there may never be an optimum size as the stall pattern may greatly vary for the two submodules involved.
It is an object of the present invention to substantially overcome, or at least ameliorate one or more deficiencies with existing arrangements.
In accordance with one aspect of the present invention there is disclosed a method of improving the performance of a pipeline system in which a FIFO is incorporated in said pipeline between an upstream processing module and a downstream processing module, each of said modules having access to a common external memory, said method being characterised by:
detecting when said FIFO is substantially full and transferring commands from said upstream module to said external memory; and
interpreting commands from each of said FIFO and said external memory to said downstream module to determine a source of following ones of said commands.
In accordance with another aspect of the present invention there is disclosed a pipelined processor system comprising:
an upstream processor module;
a downstream processor module;
a FIFO arrangement coupling an output of said upstream module to an input of said downstream module to thus form a processor pipeline;
a memory module accessible by each of said processor modules; and
an overload arrangement by which a filling of said FIFO arrangement is detected and said output of said upstream module is directed for intermediate storage in said memory module and by which said downstream module can interpret commands received from each of said FIFO arrangement and said memory module to determine a source of subsequent commands.
Other aspects of the invention are also disclosed.